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ICs for Consumer Electronics
Display Processor SDA 9280 B22
Data Sheet 1998-02-01
Edition 1998-02-01 This edition was realized using the software system FrameMaker(R) Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1998. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SDA 9280 B22 Revision History: Previous Version: Page Page (in previous (in current Version) Version) 31 33
Current Version: 1998-02-01 1997-11-01 Subjects (major changes since last revision)
ESD protection: Except: Pin 36 (SDA) 300V added
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Recommended Operating Conditions Under this conditions the functions given in the circuit description are fulfilled. Nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. If not stated otherwise, nominal values will apply at TA=25C and the nominal supply voltage. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit.
Edition 1998-02-01 Published by Siemens AG, Semiconductor Group Copyright (c) Siemens AG 1998. All rights reserved. Terms of delivery and right to change design reserved.
SDA 9280 B22
1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.12.1 2.12.2 2.12.3 2.12.4 3 3.1 3.2 4 5 5.1 5.2 5.3 5.4 5.5 6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Input Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chrominance Interpolation (Interpolator 1) . . . . . . . . . . . . . . . . . . . . . . . . . Luminance Peaking Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Color Transient Improvement (DCTI) . . . . . . . . . . . . . . . . . . . . . . . . Picture Manipulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16:9-Operation, Signal Compander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oversampling, Interpolator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Insertion Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplification, D/A Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input-Output Signal Delay Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC-Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC-Bus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC-Bus Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC-Bus Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 13 14 15 15 16 17 18 19 21 22 22 22 23 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Characteristics (Assuming Recommended Operating Conditions) . . . . . . . 36 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram Data Input Referenced to the Clock . . . . . . . . . . . . . . . . . Timing Diagram Clock Skew SCA-CLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Data Format 4:1:1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Data Format 4:2:2 Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Data Format CCIR 656 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 41 42 42
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Semiconductor Group
4
Display Processor
SDA 9280 B22
MOS 1 1.1 Overview Features
* 8-Bit amplitude resolution of each input component Input sample frequency up to 30 MHz Application in flicker reduction systems possible * Four input data formats 4:1:1 luminance and chrominance parallel P-LCC-68-1 (8 + 4 wires) 4:2:2 CCIR 656-format (8 wires) 4:2:2 luminance and chrominance parallel (2 x 8 wires) 4:4:4 all components parallel (3 x 8 wires) * Two different representations of input data Positive dual code 2's complement code * Three D/A converters on-chip 9-Bit amplitude resolution 80 MHz maximal clock frequency * DCTI (digital color transient improvement) A digital algorithm improves the sharpness of vertical color edges avoiding the artifacts of analog CTI-circuits * Luminance peaking Separate programmable lowpass, bandpass, and highpass digital filters * High performance digital interpolation for anti-imaging Two-fold oversampling Simplification of external analog postfiltering * 16:9 compatibility Signal compression for displaying 4:3-signals on16:9-screens Signal expansion for displaying 16:9-signals on 4:3-screens Full screen display of 4:3 letter box pictures
Type SDA 9280 B22
Semiconductor Group
Ordering Code Q67101-H5039-B502-35
5
Package P-LCC-68-1
1998-02-01
SDA 9280 B22
* Programmable delay for the luminance signal Phase adjustment between luminance and chrominance signals * Signal manipulations Inverted display Graphic display * Insertion of colored areas Programmable color and position * Insertion of an arbitrary pattern Control by an external signal One of 4096 colors programmable Frame insertion for multi picture display * N-Fold zoom facility for image memory systems * Programmable internal PLL for clock generation Control of compression and expansion factors * I2C-Bus control * P-LCC-68-1 package * 5 V supply voltage 1.2 General Description
The Display Processor SDA 9280 is an integrated triple 9 Bit D/A converter which performs digital enhancements and manipulations of digital video component signals. Multiple input data formats are accepted. Operation with normal as well as doubled horizontal deflection frequency is supported. 4:3 or 16:9 display formats are possible.
Semiconductor Group
6
1998-02-01
SDA 9280 B22
1.3
Pin Configuration
TEST HS CLL VS TEST SDA VSS VSS VDD
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 LF
SCL RES SCA INS BLN VSS
VSS VDD
VCCI
GNDY YQ VCCI VCCA GNDV VQ VCCI GNDU UQ GNDA V REF R REF VCC GND VSS
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
VDD
YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 VSS UV7 UV6 UV5 UV4 UV3 VDD VDD
VDD VDD VSS
V0 V1 V2 V3 V4 VSS
V5 V6 V7 UV0 UV1 UV2 VSS VSS
UEP10245
Figure 1
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SDA 9280 B22
1.4
Pin Description Symbol Type S S S Description Supply voltage (VSS) for input stages Supply voltage (VSS) for digital parts and PLL Note: no internal connection to pins No 1,17,35 Supply voltage (VDD) for digital parts, PLL and input stages Note: internal connection to VCCI, VCCA (about 2 ) Data input V (see Data Input Formats) Data input UV (see Data Input Formats) Data input YUV (see Data Input Formats) Blanking signal, high level indicates active video line Control signal for insertion of an arbitrary pattern (frame insertion) Clock signal for data input Reset signal (active low) for 2C Bus
Pin No. 1,17,35 8,9,27,34,43, 60,63 10,11,26,33, 42,61,62
VSS VSS VDD
64 ... 68, 2 ... 4 V0 ... 7 5,6,7,12 ... 16 UV0 ... 7 18 ... 25 28 29 30 31 32 36 37 38 39 40 41 44 45,48,52 46 47 49 50 BLN INS SCA RES SCL SDA TEST VS CLL HS TEST LF
I/TTL I/TTL I/TTL I/TTL I/TTL I/TTL I IQ I/TTL I/TTL I/TTL
YUV0 ... 7 I/TTL
2C-Bus clock line 2C-Bus data line
Don't connect Vertical synchronization signal for synchronizing 2C Bus (active: HIGH) System clock Control signal for black level insertion (line frequency) Connect to VSS PLL-filter connection
VCCI
GNDY YQ
S S Q/ana S S
Analog supply voltage for DACs internally connected to VDD, VCCA (about 2 ) Return path for YQ Analog output: luminance signal Y Analog supply voltage internally connected to VDD, VCCI (about 2 ) Return path for VQ
8 1998-02-01
VCCA
GNDV
Semiconductor Group
SDA 9280 B22
1.4
Pin Description (cont'd) Symbol VQ GNDU UQ GNDA Type Q/ana S Q/ana S I/ana S S Q: output, Description Analog output: chrominance signal -(R-Y) Return path for UQ Analog output: chrominance signal -(B-Y) Analog supply voltage Analog reference voltage for DACs Reference resistor for DACs Analog supply voltage Analog supply voltage TTL: digital (TTL)
Pin No. 51 53 54 55 56 57 58 59 S: supply,
VREF RREF VCC
GND I: input,
Semiconductor Group
9
1998-02-01
SDA 9280 B22
1.5
Block Diagram
VSS
10
VDD
7
GND GNDA VCC
VCCI VCCA
3 2 9 DAC 9 Bit
R REF V REF
YQ GNDY
YUV
8
8
Variable 8 Y-Delay
Peaking 9 Filter
Compander
9
Inter- 10 polator 2
Insertion
UV
8
MUX
8 Interpolator 1
9
DCTI
9
Compander
9
Inter- 10 polator 2
Insertion
9
DAC 9 Bit
UQ GNDU
V
8
8
9
9 DCTI
Compander
9
Inter- 10 polator 2
Insertion
9
DAC 9 Bit
VQ GNDV
2 C-Bus Receiver
PLL
SCA
SDA SCL RES VS INS
BLN
HS
CLL LF
UEB10244
Figure 2
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SDA 9280 B22
2 2.1
System Description Data Input Formats CCIR 656 4:2:2 INFOR = 00 Parallel INFOR = 10 Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00 U07 U06 U05 U04 U03 U02 U01 U00 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 V07 V06 V05 V04 V03 V02 V01 V00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 4:4:4 INFOR = 11 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 V07 V06 V05 V04 V03 V02 V01 V00 X: signal component A: sample number B: bit number
Input Data Format 4:1:1 Pin INFOR = 01 YUV7 Y07 YUV6 Y06 YUV5 Y05 YUV4 Y04 YUV3 Y03 YUV2 Y02 YUV1 Y01 YUV0 Y00 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 V7 V6 V5 V4 V3 V2 V1 V0 XAB: U07 U06 V07 V06 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02
The SDA 9280 accepts four different data input formats (2C signal: INFOR). Three sample frequency relations of Y:(B-Y):(R-Y) are possible (4:1:1 or 4:2:2 or 4:4:4).
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The representation of the samples is programmable separately for luminance and chrominance signals as positive dual code or 2's complement code (2C signals: INCODL, INCODC) The amplitude resolution for each input is 8 Bit, the maximal clock frequency is 30 MHz. Consequently the SDA 9280 is dedicated for applications in high quality digital video systems. The data input stages and the internal data multiplexer operate with a special data input clock (SCA). For applications in the Siemens MEGAVISION(R) System the SCA-clock is identical with the memory output clock. A separation of the data input clock and the system clock is relevant to handle the special data format occurring at "zoom" operation mode. For other applications SCA can be connected with CLL.
Note: Zoom mode causes a greater signal delay time of the whole IC. Zoom mode identification is performed automatically.
2.2 Chrominance Interpolation (Interpolator 1)
10 dB 0 -10
UED10246
Amplitude
-20 -30 -40 -50
0
0.1
0.2
0.3
0.4
0.5
f fS
Figure 3 Frequency Response of a Filter Stage of Interpolator 1 (s is the sampling frequency at the output of the interpolation filter stage) For internal processing the 4:4:4 parallel format is used. The 4:1:1 data are interpolated by two interpolation filters having the same frequency response (see figure 3) to the 4:4:4 format. Each filter performs a doubling of the sample frequency. The 4:4:4 interpolation of 4:2:2 data is done by the second filter stage. The diagram shows the frequency response of one filter stage.
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Interpolation filtering can be switched off for each stage separately (2C signals: INT422, INT444). Then each sample is simply repeated twice. Activation of interpolation filtering is recommended because analog postfiltering of chrominance signals then can be greatly simplified (see also Interpolator 2). 2.3 Luminance Peaking Filter
The luminance peaking filter improves the over all frequency response of the luminance channel. It consists of three filters working in parallel. They have low pass (LP(z)), band pass (BP(z)) and high pass (HP(z)) characteristics. Their gain factors are separately programmable (2C signals: LCOF, BCOF, HCOF) according to the following equations: LCOF * LP(z) + BCOF * BP(z) + HCOF * HP(z) with: LCOF = 0 ... [1/4] ... 3/2, 2 BCOF = 0 ... [1/4] ... 3, 7/2, 4, 5 HCOF = 0 ... [1/4] ... 3, 7/2, 4, 5 LP(z) = 1/16 * (1 + z-1)4 BP(z) = -1/8 * (1 - z-2)2 HP(z) = 1/16 * (1 - z-1)4
An amplification of up to 14 dB at the half of the sample frequency is available. The high pass and band pass filters are equipped with a common coring algorithm. It is optimized to achieve a smooth display of grey scales, not to improve the signal-to-noise ratio. Therefore no artifacts are produced. Coring can be switched off (2C signal: COR).
Note: The peaking filter may shift the black level of the signal. This has to be considered for black level insertion (see Insertion Facilities).
A delay line for the luminance signal enables an adaption to the delay of the chrominance signals. A range of -8 to +7 clock periods of the system clock CLL is programmable (2C signal: YDEL1). An additional special filtering is available for compensating a non linear phase response of the analog part of the signal path. Three adjustments are 2C-Bus programmable: PHACOM = 0, 1/4, 1/8. (1 + PHACOM) * z-1 - PHACOM
Semiconductor Group
13
1998-02-01
SDA 9280 B22
HP(z)
HCOF
YIN
BP(z)
Coring
YOUT
BCOF LP(z)
COR
LCOF
UES10247
Figure 4 Luminance Peaking 2.4 Digital Color Transient Improvement (DCTI)
A new digital algorithm is implemented to improve horizontal transitions of the chrominance signals resulting in a better picture sharpness. A slow change from one color to another by reason of small chrominance bandwidth is replaced by a steep transition. The exact position of a color transition (POS) is calculated by detecting the corresponding zero transition of the second derivative of both chrominance signals. Low pass filtering (LPU, LPV, LPUV) is performed to avoid noise sensitivity. The width of a transition is derived from a threshold detector signal. It indicates an area around the detected position where the first derivatives of the chrominance signals exceed a programmable threshold (2C signal: THRESH). The parameter THRESH modifies the sensitivity of the DCTI-circuit. High values cause that only significant color transitions are improved. Small color variations remain unchanged. The detected transition width can be limited by the programmable parameter TRAWID. This parameter performs an adaption to the input chrominance band width. For signals with small chrominance bandwidth (e.g. video recorders) the DCTI-performance is optimized using high values for TRAWID. Input signals with high chrominance bandwidth should be processed with small values for TRAWID. If standard 4:1:1 video signals are processed, it is recommended to choose values of the mid range for both parameters THRESH and TRAWID.
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SDA 9280 B22
UIN
LPU
First Derivative
Threshold WIDTH Detection
THRESH POS Zero Transition Insertion of Steep Transition UOUT VOUT
LPUV VIN LPV First Derivative
Second Derivative
Width Control
TRAWID
UES10248
Figure 5 Digital Color Transient Improvement 2.5 Picture Manipulations
A graphic display effect is realized by programmable reduction of amplitude resolution (2C signals: YGR, YGRRES, CGR, CGRRES). A resolution of 1 to 4 bits is available. A special characteristic avoids a reduction of picture brightness and color saturation. The inverted display mode is attained by a programmable bit inversion for each signal component (2C signals: YINV, UINV, VINV). Multiple combinations of both manipulations supply very amazing effects on the display. 2.6 16:9-Operation, Signal Compander
The compander enables a display with correct geometric proportions of 4:3 signals on 16:9-screens or 16:9-signals on 4:3-screens. A full screen display of 4:3-letterbox signals on 16:9-screens is also practicable. Having a full screen display of such signals on 4:3-screens only a part of the picture can be shown. In this operation mode a horizontal shift of the picture part used for display is programmable (2C signal: READD). Expansion in vertical direction must be realized by manipulation of the vertical deflection current. To satisfy all these demands a horizontal compression or expansion of the video signals is performed by raising or reducing the sample frequency. The data are written into a memory using the system clock CLL and read with a clock of higher or lower frequency.
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This realization does not effect the horizontal detail resolution of the picture because no filtering is executed. The highest read frequency is 4/3 of the CLL-frequency for signal compression, the lowest is 3/4 of the CLL-frequency for signal expansion. The reading clock is supplied by the internal PLL. The compander operation mode is programmable via 2C signals COMP and COMEX.
Note: Positioning of a 4:3-signal on a 16:9-screen is realized by delaying the HS-signal. HS also controls the deflection circuit. In the Siemens MEGAVISION(R) System a programmable HS-delay is available in the Memory Sync Controller (MSC) circuit.
2.7 Oversampling, Interpolator 2
10 dB 0 -10
UED10249
Amplitude
-20 -30 -40 -50
0
0.1
0.2
0.3
0.4
0.5
f / fS
Figure 6 Frequency Response of Interpolator 2 (s is the sampling frequency at the output of the interpolation filter) In general D/A conversion requires postfiltering to avoid non-harmonic distortions caused by intermodulations of the signal with its spectral images. These intermodulations may come from non-linear characteristics of subsequent amplifier stages or of the display. The spectral images are duplicates of the signal spectrum around multiples of the sampling frequency. These images, a counterpart of aliasing in the A/D conversion, become visible after D/A conversion. They are only reduced by the sinx/x characteristic of the D/A converter.
Semiconductor Group
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An example of such non-harmonic distortions are periodic stripes with a frequency of 900 kHz appearing in a 4.8 MHz test pattern which is sampled with 13.5 MHz clock frequency (2 * 4.8 MHz - (13.5 - 4.8) MHz = 900 kHz). The ideal postfiltering comprises an ideal lowpass filter with an edge frequency at the maximum signal frequency and a stop band rejection of at least 30 or 40 dB. In practice the postfilter can be greatly simplified when a large transition band is allowed. For this purpose a digital interpolator is implemented with a steep transition at the half of the sampling frequency and an out of band rejection of more than 30 dB before D/A conversion. Combined with a two-fold oversampling the first image appears around twice the sampling frequency, thus leaving considerably more space for the transition band of an analog postfilter. There is another good reason for using a digital interpolation. Since the output frequency may vary with different compression or expansion factors an analog filter with varying edge frequencies is necessary. This requirement can only be fulfilled in the digital domain because the edge frequency is linearly controlled by the sample frequency. The amplification factor of the implemented interpolation filter is 65/64. The maximal output clock frequency is 8/3 times of the input sample frequency. The diagram (figure 6) shows the frequency response. Oversampling can be switched off (2C signal: OVSAMP). Then the 4:4:4 format is directly D/A converted. With activated oversampling it is possible to switch off oversampling filtering (2C signal: OVFILT). In this operation mode the input clock frequency is doubled but each sample is simply repeated twice. 2.8 Insertion Facilities
Three different values are inserted into the video signal: black level, a colored background area and an arbitrary colored pattern. The blanking interval of the input signal is not processed by the compander. Therefore the black level shifting in the luminance signal, caused by the peaking filter (coefficient LCOF) and the amplification factor of the oversampling filter, has to be restored by inserting the correct value (BLACK). BLACK is programmable and must be computed according to the coding of the input data using the following formulas: BLACK = 128 + 65/128 * LCOF * (BLACKIN - 128) BLACK = 128 + 65/128 * LCOF * BLACKIN for positive dual coding for 2's complement
BLACKIN is the black level of the input signal, LCOF is the Lowpass coefficient of the Luminance Peaking Filter: 0 ... [1/4] ... 1.5, 2 Black level insertion is controlled by the external signal HS. This signal also controls the deflection circuit, consequently it has a stable phase referring to the horizontal blanking interval. The value BLACK is inserted during 80 clock periods of the clock CLL. In the Siemens MEGAVISION(R) System HS is supplied by the MSC-circuit. To adjust the right insertion phase a programmable delay of HS is available (2C signal: HSDEL).
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The second insertion facility produces a colored background area on the display controlled by 2C Bus. Activating this insertion mode (2C signal: BACKGR) parts of the display area are covered with a constant color (2C signals: COLBY, COLBU, COLBV). Starting at a programmable pixel position of each line (2C signal: BCKPOS) the following part is covered with the background values. The width of the insertion is also programmable (2C signal: BCKWID). To realize for example two vertical background stripes at the left and right side of the display BCKPOS should be set to a high value. Then the background color is inserted over the blanking interval (except the black level phases) up to the first active pixels of the following line fixed by BCKWID. An example for application is the display of a 4:3-picture on a 16:9-screen. The free parts of the display and also the noisy start and end of the picture can be filled with background color. An opening and closing curtain can also be realized using background insertion mode. Insertion of an arbitrary pattern is controlled by the external signal INS. The color of the pattern is programmable (2C signals: COLFY, COLFU, COLFV). The insertion raster corresponds to the 4:4:4 format. A fixed phase to the video signal is guaranteed by processing the INS-signal by the compander. Using this insertion mode a colored framing for multi-picture mode can be realized. The MSC of the Siemens MEGAVISION(R) System supplies a suited signal (FRM). A connection of the BLN2-signal supplied by the MSC to the INS-input enables a complete blanking of the horizontal and vertical inactive parts of the video signal. The polarity of the INS-signal is programmable by 2C Bus (INSNEG). All insertions are performed after oversampling resulting in sharp transitions without overshooting. 2.9 Amplification, D/A Conversion
Before D/A conversion a fine adjustment of the phase of the luminance signal is performed (2C signal: YDEL2). The delay of the luminance signal can be varied by one period of the D/A converter clock. The amplification factors of each signal component can be reduced by a factor of 0.5 (2C signals: AMPY, AMPU, AMPV). This reduction of nominal amplification reserves one bit for D/A conversion of overshooting, resulting from strong peaking or interpolation filtering. The input amplitude resolution of 8 Bit is not reduced. For conversion of signals without or with only small overshooting a reduction of the amplification factor is not necessary. A digital limiter circuit prevent the D/A converters from possible overdriving by clipping.
Note: Clipping causes a non-linear deformation with interferences between multiples of the signal frequency and the sample rate of the signal and should be avoided by reducing the amplification factor.
A triple 9 Bit D/A converter is implemented on the SDA 9280. The DACs are short circuit protected converters with current outputs.
Semiconductor Group
18
1998-02-01
SDA 9280 B22
The Full Range Output Current of the Y, U, and V channels (IOFR) is determined by the current IREF at the RREF pin by
IOFR (4/3) IREF
The voltage at pin RREF is generated via pin VREF by an internal operational amplifier and follows the voltage at pin VREF. Thus IREF is given by
IREF VVREF/RREF where RREF is a resistor between pin RREF and analog ground. Another way to define IREF is the application of a current sink at the RREF point. For recommended values of VVREF and IREF see chapter 'Recommended Operation Conditions'. For applications with lower requirements there is still another way to define IOFR: Connect pin VREF to the positive
supply and apply a resistor against ground. Since in this operation mode the internal reference amplifier goes into saturation, the exact value of IREF is not so well predictable 2.10 PLL Circuit
/2
Divider DIVVCO Phase Discriminator Reference Clock Divider DIVREF LF VCO Output Clock
UES10250
Figure 7 The internal PLL supplies the clock signals needed for compander operation, output processing and D/A conversion. The output frequency of the PLL is defined by programming the divider factors of the reference clock and of the VCO clock (2C signals: DIVREF, DIVVCO). The PLL always supplies the frequency needed for oversampling. The clocks used in the other output processing parts are derived from this oversampling clock. Even if no oversampling is programmed (OVSAMP = 0) DIVREF
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and DIVVCO must be set according to the respective oversampling frequency. The reference clock of the PLL is the system clock CLL. The output frequency of the PLL fOUTPUT is calculated by the following equation:
fOUTPUT = fREFERENCE * (2 * DIVVCO) / DIVREF
Note: An arbitrary setting of the output frequency is not allowed. It has to be observed that there is resulting an integer number of clock periods per line. E.g. the input signal has 858 clock periods per line, 3:4 signal expansion results in 858 * 3/4 = 643.5 clock periods per line, which is not an integer number. Therefore this adjustment results in phase jumps of the output clock and in an unstable working condition of the PLL.
The following table gives an overview of possible PLL modes referred to an input signal with 864 pixels per line and a clock frequency of 13.5 MHz. Compression-/ Resulting Clock ExpansionPeriods per Factor Line 4:3 5:4 11:9 7:6 9:8 10:9 13:12 1:1 15:16 11:12 8:9 7:8 5:6 13:16 7:9 3:4 1152 1080 1056 1008 972 960 936 864 810 792 768 756 720 702 672 648 Compander Read Frequency [MHz] 18 16.875 16.5 15.75 15.1875 15 14.625 13.5 12.65625 12.375 12 11.8125 11.25 10.96875 10.5 10.125 DIVVCO DIVREF
4 5 11 7 9 10 13 4 15 11 8 7 5 13 7 3
3 4 9 6 8 9 12 4 16 12 9 8 6 16 9 4
The PLL circuit can be switched inactive (2C signal: PLLON). In this mode the system clock is also used for output processing and D/A conversion.
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To achieve an optimal PLL operation an adaption to the required frequency range can be programmed (2C signal: PLLRAN). 2.11 Input-Output Signal Delay Time
Due to several digital signal processing stages transients of the digital input signal at the YUV inputs appear with a certain delay at the analog YUV outputs. In the following table are defined the values for two typical circuit configurations. The configuration of the circuit is defined as the total configuration of all programmable signal processing stages on the device, the programming itself is performed via the 2C Bus. Name Internal PLL Compander Oversampling Input data format Zoom Internal PLL Function Switched OFF (Subaddress 10H, Bit D5 ... D0 = 00 0000) Bypassed (Subaddress 06H, Bit D1 = 0) No (Subaddress 07H, Bit D1 ... D0 = 00) (Subaddress 00H, Bit D5 ... D4 = 01 or 10 or 11) No (frequency of SCA and CLL is identical) Switched ON 126 CLL typ (Subaddress 10H, Bit D5 ... D0 = 00 0010) (Subaddress 14H, Bit D7 ... D0 = 0100 0100) Active without compression or expansion (Subaddress 06H, Bit D0 = 0) (Subaddress 06H, Bit D7 ... D2 = 000001) Yes (Subaddress 07H, Bit D1 ... D0 = 11) (Subaddress 00H, Bit D5 ... D4 = 01 or 10 or 11) No (frequency of SCA and CLL is identical) Time delay 120 CLL typ
Compander
Oversampling Input data format Zoom
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2.12
I2C-Bus Control
2.12.1 I2C-Bus Address 0010110 2.12.2 I2C-Bus Format write: S00101100A read: S00101101A Data Byte n A Data Byte (n+1) A ***** NA P Subaddress A Data Byte A ***** A P
Reading starts at the last write address n. Specification of a subaddress in reading mode is not possible. S: A: P: NA: Start condition Acknowledge Stop condition Not acknowledge
An automatical address increment function is implemented. After switching on the IC (RES = 0), all bits are set to defined states. Except the following bits the reset state is "0". The bits YDEL13, BCOF2, LCOF2, HCOF2, DIVREF2, DIVVCO2 are set to "1" to ensure a basic working condition. In order to avoid distortions of the picture during the active lines, the following bits are updated internally only during the HIGH-phase of VS (the programming of the 2C-Bus interface however is not affected by this synchronisation): Subaddress 00H 02H 03H 04H 05H 06H Bit D1 ... D0 D4 ... D0 D7 ... D0 D6 ... D0 D6 ... D0 D7 ... D0 Subaddress 07H 09H 0AH 0BH 0FH Bit D2 ... D0 D7 ... D0 D7 ... D0 D6 ... D0 D0
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2.12.3 I2C-Bus Commands
Data Byte Subadd. (Hex.) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H D7 INSNEG D6 0 D5 INFOR1 D4 INFOR0 THRESH0 CGR YINV LCOF0 D3 INCODL TRAWID3 D2 INCODC TRAWID2 D1 INT422 TRAWID1 D0 INT444 TRAWID0 VINV YDEL10 BCOF0 HCOF0 COMEX OVSAMP HSDEL0
THRESH3 THRESH2 THRESH1 0 YGR 0 0 READD5 0 0 0 0
CGRRES1 CGRRES0 UINV YDEL13 BCOF3 YDEL12 BCOF2 HCOF2 READD0 BACKGR HSDEL2 YDEL11 BCOF1 HCOF1 COMP OVFILT HSDEL1
YGRRES1 YGRRES0 LCOF2 COR READD4 0 0 LCOF1
PHACOM1 PHACOM0 HCOF3 READD3 0 HSDEL5 READD2 0 HSDEL4 BCKPOS4 BCKWID4 BLACK4 COLFY0 COLFU0 COLFV0 0 0 0 0 0 DIVREF0 READD1 0 HSDEL3
BCKPOS7 BCKPOS6 BCKPOS5 BCKWID7 0 COLFY3 COLFU3 COLFV3 0 PLLRAN1 0 0 0 DIVREF3 BCKWID6 BLACK6 COLFY2 COLFU2 COLFV2 0 PLLRAN0 1 0 0 DIVREF2 BCKWID5 BLACK5 COLFY1 COLFU1 COLFV1 0 0 0 0 0 DIVREF1
BCKPOS3 BCKPOS2 BCKPOS1 BCKPOS0 BCKWID3 BLACK3 COLBY3 COLBU3 COLBV3 AMPY 0 0 0 0 DIVVCO3 BCKWID2 BLACK2 COLBY2 COLBU2 COLBV2 AMPU 0 0 0 0 DIVVCO2 BCKWID1 BLACK1 COLBY1 COLBU1 COLBV1 AMPV PLLON 0 0 1 DIVVCO1 BCKWID0 BLACK0 COLBY0 COLBU0 COLBV0 YDEL2 0 0 0 0 DIVVCO0
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2.12.4 Detailed Description Subaddress 00H: Interpolation Mode and Input Format Bit D0 Name INT444 Function 4:4:4 Interpolation filtering: 0: interpolation 4:2:2 -> 4:4:4 OFF 1: interpolation 4:2:2 -> 4:4:4 ON 4:2:2 Interpolation filtering: 0: interpolation 4:1:1 -> 4:2:2 OFF 1: interpolation 4:1:1 -> 4:2:2 ON Coding of chrominance input data: 0: positive dual code 1: 2's complement Coding of luminance input data: 0: positive dual code 1: 2's complement Input data format: 00: CCIR 656 01: 4:1:1luminance, chrominance parallel (8 + 4 wires) 10: 4:2:2luminance, chrominance parallel (2 x 8 wires) 11: 4:4:4all components parallel (3 x 8 wires) No function assigned. Assign binary value: 0 INSNEG Polarity of INS input signal: 0: positive polarity 1: negative polarity
D1
INT422
D2
INCODC
D3
INCODL
D5, D4
INFOR
D6 D7
Subaddress 01H: Digital Color Transition Improvement Control Bit D3 ... D0 Name TRAWID Function DCTI: 0000: 0001: : 1100: maximal length of an improved transition: DCTI OFF 2 pixel : 24 pixel sensitivity threshold: lowest threshold (highest sensitivity) : highest threshold (lowest sensitivity)
D7 ... D4
THRESH DCTI: 0000: : 1111:
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Subaddress 02H: Color Feature Control Bit D0 Name VINV Function Inversion of (R-Y)-signal: 0: inversion OFF 1: inversion ON Inversion of (B-Y)-signal: 0: inversion OFF 1: inversion ON
D1
UNIV
D3, D2
CGRRES Amplitude resolution of chrominance signals (CGR = 1): 00: 1 Bit 01: 2 Bit 10: 3 Bit 11: 4 Bit CGR Chrominance graphic display: 0: OFF 1: ON No function assigned. Assign binary value : 000
D4
D7 ... D5
Subaddress 03H: Luminance Feature Control Bit D3 ... D0 Name YDEL1 Function Delay adjustment of luminance signal: 0000: -8 clock periods (CLL) 0001: -7 clock periods (CLL) : : 1000: no delay : : 1111: +7 clock periods (CLL) Inversion of luminance signal: 0: inversion OFF 1: inversion ON
D4
YINV
D6, D5
YGRRES Amplitude resolution of luminance signal (YGR = 1): 00: 1 Bit 01: 2 Bit 10: 3 Bit 11: 4 Bit YGR Luminance graphic display: 0: OFF 1: ON
25 1998-02-01
D7
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SDA 9280 B22
Subaddress 04H: Luminance Peaking Control Bit D3 ... D0 Name BCOF Function Luminance peaking, gain of band pass filter: 0000: 0 0001: 1/4 : : : [1/4] : : 1100: 12/4 1101: 14/4 1110: 16/4 1111: 20/4 Luminance peaking, gain of low pass filter: 000: 0 001: 1/4 : : : [1/4] : : 110: 6/4 111: 8/4 No function assigned. Assign binary value: 0
D6 ... D4
LCOF
D7
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Subaddress 05H: Luminance Peaking Control Bit D3 ... D0 Name HCOF Function Luminance peaking, gain of high pass filter: 0000: 0 0001: 1/4 : : : [1/4] : : 1100: 12/4 1101: 14/4 1110: 16/4 1111: 20/4
D5, D4
PHACOM Filter coefficient for compensation of non-linear phases: 00: 0 01: 1/8 10: 2/8 COR Luminance peaking, coring for high- and band-pass filter: 0: OFF 1: ON No function assigned. Assign binary value: 0
D6
D7
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Subaddress 06H: Compander Control Bit D0 Name COMEX Function Compander working condition: 0: signal compression 1: signal expansion
Note: For oversampling without compression or expansion COMEX = 0 is recommended in order to minimize the signal delay time.
D1 COMP Compander activation: 0: bypass 1: compander active Compander, displayed picture part: (shifting raster: 4 pixels) 000000: not recommended 000001: left part of the picture : : 111111: right part of the picture
D7 ... D2
READD
Note: For signal compression READD = 101101 is required. For oversampling without compression or expansion READD = 000001 is required.
Subaddress 07H: Oversampling Control (Interpolator 2) and Background Activation Bit D0 Name Function OVSAMP Oversampling control: 0: doubling of sample frequency OFF 1: doubling of sample frequency ON OVFILT Oversampling control (OVSAMP = 1): 0: interpolation filtering OFF 1: interpolation filtering ON
D1
D2
BACKGR Activation of background insertion: 0: insertion OFF 1: insertion ON No function assigned. Assign binary value: 00000
D7 ... D3
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Subaddress 08H: Black Level Insertion Control Bit D5 ... D0 Name HSDEL Function Start of black level insertion, delay to HS-signal: 000000: no delay 000001: 16 clock periods (CLL) delay : : 111111: 1008 clock periods (CLL) delay
Note: If HSDEL is greater than the number of samples per line there is no insertion of black level.
D7 ... D6 No function assigned. Assign binary value: 00
Subaddress 09H: Background Insertion Control Bit D7 ... D0 Name Function BCKPOS Background insertion, positioning of inserted area: 00000000:starting at pixel 290 00000001:starting at pixel 292 : : 11111111:starting at pixel 800
Subaddress 0AH: Background Insertion Control Bit D7 ... D0 Name BCKWID Function Background insertion, horizontal width of inserted area: 00000000:136 pixel 00000001:140 pixel : : 11111111:1156 pixel
Note: If BCKWID is greater than the number of pixels per line the whole line is filled with background color.
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Subaddress 0BH: Black Level Coding Bit D6 ... D0 Name BLACK Function Coding of inserted black level (Y-channel), computation see chapter `Insertion Facilities': 0000000: 0 0000001: 1 : : 1111111: 127 No function assigned. Assign binary value: 0
D7
Subaddress 0CH: Background Color/Y Signal Bit D3 ... D0 D7 ... D4 Name COLBY COLFY Function Background color (luminance):4 MSBs Color of inserted pattern (luminance):4 MSBs
Subaddress 0DH: Background Color/B-Y Signal Bit D3 ... D0 D7 ... D4 Name COLBU COLFU Function Background color (B-Y):4 MSBs Color of inserted pattern (B-Y):4 MSBs
Subaddress 0EH: Background Color/R-Y Signal Bit D3 ... D0 D7 ... D4 Name COLBV COLFV Function Background color (R-Y):4 MSBs Color of inserted pattern (R-Y):4 MSBs
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Subaddress 0FH: Signal Amplification Bit D0 Name YDEL2 Function Delay fine adjustment of luminance signal: 0: no delay 1: 1 D/A converter clock period Amplification of (R-Y) signal path: 0: amplification = 0.5 1: amplification = 1 Amplification of (B-Y) signal path: 0: amplification = 0.5 1: amplification = 1 Amplification of luminance signal path: 0: amplification = 0.5 1: amplification = 1 No function assigned. Assign binary value: 0000
D1
AMPV
D2
AMPU
D3
AMPY
D7 ... D4
Subaddress 10H: PLL Control Bit D0 D1 PLLON Name Function No function assigned. Assign binary value: 0 Activation of internal PLL: 0: PLL OFF 1: PLL ON No function assigned. Assign binary value: 0000 PLLRAN Frequency range of internal PLL: 00: 9 ... 13 MHz 01: 11 ... 40 MHz 10: 29 ... 60 MHz 11: 44 ... 80 MHz
D5 ... D2 D7, D6
Subaddress 11H: Test Control Bit D7 ... D0 Name TEST11 Function Only for test conditions
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Subaddress 12H: Test Control Bit D7 ... D0 Name TEST12 Function Only for test conditions
Subaddress 13H: Test Control Bit D7 ... D0 Name TEST13 Function Only for test conditions
Subaddress 14H: PLL Control/VCO and Reference Clock Bit D3 ... D0 Name DIVVCO Function PLL-frequency programming, divider of VCO-clock: 0000: 16 0001: not allowed 0010: 2 : : 1111: 15 PLL-frequency programming, divider of reference clock: 0000: 16 0001: not allowed 0010: 2 : : 1111: 15
D7 ... D4
DIVREF
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3
Absolute Maximum Ratings Symbol 0 -65 Limit Values min. max. 70 125 125 260 10 C C C C s Unit Remark
Parameter
Operating temperature TA
Tstg Junction temperature Tj Soldering temperature TS
Storage temperature Soldering time Input voltage Output voltage Supply voltages Supply voltage differentials
VI VQ VDD
-0.3 V VDD + 0.3 V 1 -0.3 V VDD + 0.3 V 1 -0.3 -0.25 6 0.25 V V
VCC respectively VCC respectively
Between any internally non-connected supply pins of the same kind, see Pin Description For any single output For any single output MIL STD 883C method 3015.6, 100 pF, 1500 Except: Pin 36 (SDA) 300 V All inputs/outputs
DAC output current
-30 -30 1.7 -2 2
mA mA W kV
RREF output current
Total power dissipation Ptot ESD protection
Latch-up protection
-100
100
mA
All voltages listed are referenced to ground (0 V, VSS) except where noted.
Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied.
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3.1
Recommended Operating Conditions Symbol min. 4.75 0 2.0 0 0.02 10 10 6 10 10 0 4.5 54 -14 2.1 15 80 -11 2.4 27 30 27 Limit Values nom. 5 25 max. 5.25 70 V C V V MHz ns ns MHz ns ns ns MHz mA V V V kHz Diagram on page 40 Rise/fall time 5 ns Rise/fall time 5 ns Unit Remark
Parameter Supply voltages
VDDxx VCCxx Ambient temperature TA
All TTL Inputs H-input voltage
L-input voltage
VIH VIL
VDD
0.8 30
Serial Clock TTL Input SCA SCA clock frequency fSCA SCA low time SCA high time CLL clock frequency CLL low time CLL high time SCA-CLL skew time DAC sample rate
tLOW tHIGH fCLL tLOW tHIGH tSK
Line Locked Clock TTL Input CLL
Digital to Analog Conversion
RREF output current VREF input voltage
H-input voltage
IREF VVREF
-17 1.8 3 0 0 4.7 4.7 4.0 4.7
I2C Bus (All Values are Referred to min.(VIH) and max.(VIL))
VIH L-input voltage VIL SCL clock frequency fSCL Inactive time before tBUF
start of transmission Set-up time start condition Hold time start condition SCL low time
VDD
1.5 100
s s s s
34 1998-02-01
tSU;STA tHD;STA tLOW
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SDA 9280 B22
3.1
Recommended Operating Conditions (cont'd) Symbol min. Limit Values nom. max. 4.0 250 0 1 300 4.7 3 Unit Remark
Parameter SCL high time Set-up time DATA Hold time DATA SDA/SCL rise times SDA/SCL fall times Set-up time stop condition L-output current
tHIGH tSU;DAT tHD;DAT tR tF tSU;STO IOL
s s s s
ns
s
mA
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3.2
Characteristics (Assuming Recommended Operating Conditions) Symbol Limit Values Unit min. max. 320 mA All VCC and VDD pins Remark
Parameter Average supply current Input capacitance
ICC
All Digital Inputs (Including I/O Inputs)
CI
-10 7
10 10
pF
Not tested; max. 7 pF for SCA, CLL
Input leakage current II(L) Set-up time Input hold time
A
ns See timing diagram 5.1 on page 40 See timing diagram 5.1 on page 40
TTL Inputs: YUV, UV, V (Referenced to SCA); BLN, INS (Referenced To CLL)
tSU tIH
6
ns
TTL Inputs: VS, HS, RES (Asynchronous to any Clock) VS low time VS high time HS low time HS high time RES low time Low-level output voltage PLL: Pin LF (Analog) Loop filter charge Pump current 150 -800 800 -150 -16.5 1 10
tLOW tHIGH tLOW tHIGH tLOW VOL
4 4 12 12 100 0.5
s s
1 1 ns V CLL periods CLL periods For reliable reset At IOL = max
Input/Output: SDA (Referenced to SCL; Open Drain Output)
A A
mA mA
VLF = 2 V VLF = 2 V VVREF = nom, TA = nom, IREF = nom, RL = 75 VVREF = nom, TA = nom, IREF = nom, RL = 75
Digital to Analog Conversion (9 Bit): Current Source Outputs YQ, UQ, VQ Full range output current Full range output current matching Temperature dependency of IOFR
IOFR
-19.5 -1 -10
A/C Not tested; VVREF = nom, IREF = nom, RL = 75
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3.2
Characteristics (Assuming Recommended Operating Conditions) (cont'd) Symbol Limit Values Unit min. max. 0.2 mA/V k -0.2 20 Remarky
Parameter Supply voltage dependency of IOFR Current source output resistance Full range output voltage DC differential nonlinearity DC integral nonlinearity Offset voltage between VREF and
VVREF = nom, TA = nom, IREF = nom, RL = 75
Not tested; VVREF = nom, TA = nom, IREF = nom
1.6 DLE ILE -1 -2 1 2
V LSB LSB
VVREF = nom, TA = nom, IREF = nom, ||LE| max
DAC Reference Pins: VREF, RREF (Analog)
VVREF VRREF
-40
40
mV
RREF VREF input current
-10
10
A
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4
Application Information
10 VDD 11 VDD 8 VSS 9 VSS 1 VSS 26 VDD
100 nF
25 YUV7 24 YUV6 23 YUV5 22 YUV4
10 H 5V 100 nF 10 F
VSS VSS VDD
27 17 33
21 YUV3 20 YUV2 19 YUV1 18 YUV0
34 VSS 35 VSS 42 VDD
100 nF
VSS
43
100 nF
61 VDD 62 VDD 16 UV7 15 UV6 14 UV5 13 UV4 60 VSS 63 VSS 58 VCC GND 59
100 nF 10 H 100 nF 10 H 100 nF 13 k 10 H
SDA 9280
45 VCCI 48 VCCI 52 VCCI 49 VCCA 56 V REF 57 R REF 150 55 GNDA 54 UQ 53 51 78 GNDV YQ 50 47 39 46 GNDY 44 LF
12 UV3 7 UV2 6 UV1 5 UV0
100 nF 10 k 100 nF 10 H 10 nF - (B-Y) 100
4 3 2 68 67 66 65 64
V7 V6 V5 V4 V3 V2 V1 V0
GNDU VQ
10 nF - (R-Y)
47 nF Y
30 SCA 29 INS 31 RES 28 BLN
HS VS CLL SCL SDA
6.2 - 6.8 k 1.5 nF
UES10251
Figure 8 This application circuit is part of a Siemens MEGAVISION(R) application
Note: The input data format must be selected via I2C Bus. Input data pins which are not used for the selected format should be connected to GND.
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40 38 39 32 36
SDA 9280 B22
Block Diagram of Standard Version
ADC Decimation 4
Noise Reduction Cross Color Reduction Multipicture Decimation 4 4 4 4 4 Picture Processor 2 SDA 9290 4 4 4
Flicker Reduction Still Picture Zoom Multipicture 4:0:0 Luminance SDA 9251X 4:0:0 Luminance SDA 9251X 4:1:1 Chrominance SDA 9251X 4:2:2 Chrominance SDA 9251X 4 4 4 4
Peaking CTI 16:9 Compansion Interpolation DAC
YI
4
YOUT
4 UI 3ADC SDA 9205-2
4
Display UOUT Processor SDA 9280
VI
4
4
VOUT
4
4
SYNC
CSG SDA 9257
SYNC
MSC3 SDA 9220
SYNCOUT
UEB10252
Figure 9
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5 5.1
Waveforms Timing Diagram Data Input Referenced to the Clock
T
t WH
Clock Input
t WL V IH t THL t TLH V IL
Input Data
V IH t SU t IH V IL
UET10253
Figure 10 5.2 Timing Diagram Clock Skew SCA-CLL
T
t WH
CLL
t WL V IH t THL t TLH V IL
t SK
T
t WH
SCA
t WL V IH t THL t TLH V IL
UET10254
Figure 11
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SDA 9280 B22
5.3
Input Data Format 4:1:1
144 138 BLN
Active Line: 720
50 Hz - Standard: 864 *TCLL 60 Hz - Standard: 858 *TCLL
SCA
BLN
YUV7...0
Y0n
Y1n
Y2n
Y3n
Y4n
Y5n
Y6n
Y7n
Y8n
Y9n
Y10n
Y11n
Y12n
Y13n
UV7
U07
U05
U03
U01
U17
U15
U13
U11
U27
U25
U23
U21
U37
U35
UV6
U06
U04
U02
U00
U16
U14
U12
U10
U26
U24
U22
U20
U36
U34
UV5
V07
V05
V03
V01
V17
V15
V13
V11
V27
V25
V23
V21
V37
V35
UV4
V06
V04
V02
V00
V16
V14
V12
V10
V26
V24
V22
V20
V36
V34
UET10255
Figure 12
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SDA 9280 B22
5.4
Input Data Format 4:2:2 Parallel
144 138 Active Line: 720
BLN 50 Hz - Standard: 864 *TCLL 60 Hz - Standard: 858 *TCLL
SCA
BLN
YUV7...0
Y0n
Y1n
Y2n
Y3n
Y4n
Y5n
Y6n
Y7n
Y8n
Y9n
Y10n
Y11n
Y12n
Y13n
UV7...0
U0n
V0n
U1n
V1n
U2n
V2n
U3n
V3n
U4n
V4n
U5n
V5n
U6n
V6n
UET10256
Figure 13 5.5 Input Data Format CCIR 656
144 138 BLN
Active Line: 720
50 Hz - Standard: 864 *TCLL 60 Hz - Standard: 858 *TCLL
SCA
BLN
YUV7...0
U0n
Y0n
V0n
Y1n
U1n
Y2n
V1n
Y3n
U2n
Y4n
V2n
Y5n
U3n
Y6n
UET10257
Figure 14
Note: XAB:
X: signal component
A: sample number
42
B: Bit number
1998-02-01
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SDA 9280 B22
6
Package Outlines
P-LCC-68-1 (Plastic Leaded Chip Carrier)
5.08 max
0.5 min 3.5 0.2
1.2 x 45 0.2
1.27 0.43 0.1
0.81 max 0.18 M A-B D 68x 20.32 D 0.1
23.3 0.3 24.21 0.07 1) 25.28 -0.26
0.38 M A-B D 34x
A
B
0.5 x 45 3x
68 1
1.1 x 45
Index Marking
24.21 0.07 1) 25.28 -0.26
1) Does not include plastic or metal protrusions of 0.15 max per side
GPL05099
Figure 15
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information".
SMD = Surface Mounted Device Semiconductor Group 43 Dimensions in mm 1998-02-01

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